riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

rocket: TIMs should never be cached

Browse Source
This commit is contained in:
Henry Cook committed 2017-10-11 18:22:52 -07:00
1 parent b64609bfe8
commit 66e4bfc2d9
4 files changed
+6 -5
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/main/scala/rocket/ICache.scala
+1 -1
View File
@@ -59,7 +59,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
Seq(TLManagerParameters(
address = Seq(AddressSet(itimAddr, size-1)),
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
regionType = RegionType.UNCACHEABLE,
executable = true,
supportsPutFull = TransferSizes(1, wordBytes),
supportsPutPartial = TransferSizes(1, wordBytes),