riscv/rocket-chip
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rocket: TIMs should never be cached

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This commit is contained in:
Henry Cook
2017-10-11 18:22:52 -07:00
parent b64609bfe8
commit 66e4bfc2d9
4 changed files with 6 additions and 5 deletions
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2
src/main/scala/rocket/ICache.scala
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@ -59,7 +59,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
Seq(TLManagerParameters(
address = Seq(AddressSet(itimAddr, size-1)),
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
regionType = RegionType.UNCACHEABLE,
executable = true,
supportsPutFull = TransferSizes(1, wordBytes),
supportsPutPartial = TransferSizes(1, wordBytes),

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -18,7 +18,7 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics:
Seq(TLManagerParameters(
address = List(address),
resources = device.reg("mem"),
regionType = RegionType.UNCACHED,
regionType = RegionType.UNCACHEABLE,
executable = true,
supportsArithmetic = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,
supportsLogical = if (usingAtomics) TransferSizes(4, coreDataBytes) else TransferSizes.none,