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Regression: fix-up address lookup

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This commit is contained in:
Wesley W. Terpstra 2016-09-15 16:16:36 -07:00
parent 30fa4ea956
commit 669e3b0d96
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/coreplex/TestConfigs.scala
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@ -23,7 +23,7 @@ class WithComparator extends Config(
case BuildGroundTest => case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p)) (p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters( case ComparatorKey => ComparatorParameters(
targets = Seq("mem", "io:ext:testram").map(name => targets = Seq("mem", "io:ext:TL2:testram").map(name =>
site(GlobalAddrMap)(name).start.longValue), site(GlobalAddrMap)(name).start.longValue),
width = 8, width = 8,
operations = 1000, operations = 1000,

2
src/main/scala/groundtest/Regression.scala
View File

@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true) io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("io:ext:bootrom").start) io.cache.req.bits.addr := UInt(addrMap("io:ext:TL2:bootrom").start)
io.cache.req.bits.typ := UInt(log2Ceil(32 / 8)) io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
io.cache.req.bits.cmd := M_XRD io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0) io.cache.req.bits.tag := UInt(0)