From 669e3b0d96a24486a3c34263ac7a996770827999 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 15 Sep 2016 16:16:36 -0700 Subject: [PATCH] Regression: fix-up address lookup --- src/main/scala/coreplex/TestConfigs.scala | 2 +- src/main/scala/groundtest/Regression.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/TestConfigs.scala b/src/main/scala/coreplex/TestConfigs.scala index e2e2fd03..2a4f4f6d 100644 --- a/src/main/scala/coreplex/TestConfigs.scala +++ b/src/main/scala/coreplex/TestConfigs.scala @@ -23,7 +23,7 @@ class WithComparator extends Config( case BuildGroundTest => (p: Parameters) => Module(new ComparatorCore()(p)) case ComparatorKey => ComparatorParameters( - targets = Seq("mem", "io:ext:testram").map(name => + targets = Seq("mem", "io:ext:TL2:testram").map(name => site(GlobalAddrMap)(name).start.longValue), width = 8, operations = 1000, diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala index ef9eb576..3eb37eed 100644 --- a/src/main/scala/groundtest/Regression.scala +++ b/src/main/scala/groundtest/Regression.scala @@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()( io.mem.grant.ready := Bool(true) io.cache.req.valid := !get_sent && started - io.cache.req.bits.addr := UInt(addrMap("io:ext:bootrom").start) + io.cache.req.bits.addr := UInt(addrMap("io:ext:TL2:bootrom").start) io.cache.req.bits.typ := UInt(log2Ceil(32 / 8)) io.cache.req.bits.cmd := M_XRD io.cache.req.bits.tag := UInt(0)