riscv/rocket-chip
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Reduce fanout on frontend io.cpu.req.valid signal

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This commit is contained in:
Andrew Waterman 2017-08-06 17:38:51 -07:00
parent 7d94074b05
commit 658e36f98b
1 changed files with 2 additions and 2 deletions
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src/main/scala/rocket/Frontend.scala
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@ -119,8 +119,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
val s2_redirect = Wire(init = io.cpu.req.valid) val s2_redirect = Wire(init = io.cpu.req.valid)
s2_valid := false s2_valid := false
when (!s2_replay && !s2_redirect) { when (!s2_replay) {
s2_valid := true s2_valid := !s2_redirect
s2_pc := s1_pc s2_pc := s1_pc
s2_speculative := s1_speculative s2_speculative := s1_speculative
s2_tlb_resp := tlb.io.resp s2_tlb_resp := tlb.io.resp