From 658e36f98b4f40b407c30f36d9cf47cc71a2e267 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Sun, 6 Aug 2017 17:38:51 -0700
Subject: [PATCH] Reduce fanout on frontend io.cpu.req.valid signal

---
 src/main/scala/rocket/Frontend.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala
index 8e545708..b4088bfe 100644
--- a/src/main/scala/rocket/Frontend.scala
+++ b/src/main/scala/rocket/Frontend.scala
@@ -119,8 +119,8 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
 
   val s2_redirect = Wire(init = io.cpu.req.valid)
   s2_valid := false
-  when (!s2_replay && !s2_redirect) {
-    s2_valid := true
+  when (!s2_replay) {
+    s2_valid := !s2_redirect
     s2_pc := s1_pc
     s2_speculative := s1_speculative
     s2_tlb_resp := tlb.io.resp