riscv/rocket-chip
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rename queue to Queue

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fixes build with case-insensitive file system
This commit is contained in:
Andrew Waterman 2012-08-08 22:11:32 -07:00
parent 17dc2075dd
commit 6546dc84e2
4 changed files with 6 additions and 6 deletions
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2
uncore/llc.scala
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@ -245,7 +245,7 @@ class LLCData(latency: Int, sets: Int, ways: Int, leaf: Mem[Bits]) extends Compo
val isWriteback = Bool() val isWriteback = Bool()
override def clone = new QEntry().asInstanceOf[this.type] override def clone = new QEntry().asInstanceOf[this.type]
} }
val q = (new queue(latency+2)) { new QEntry } val q = (new Queue(latency+2)) { new QEntry }
val qReady = q.io.count <= UFix(q.entries-latency-1) val qReady = q.io.count <= UFix(q.entries-latency-1)
val valid = Reg(resetVal = Bool(false)) val valid = Reg(resetVal = Bool(false))
val req = Reg() { io.req.bits.clone } val req = Reg() { io.req.bits.clone }

2
uncore/memserdes.scala
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@ -149,7 +149,7 @@ class MemDessert extends Component // test rig side
io.wide.req_data.valid := state === s_data io.wide.req_data.valid := state === s_data
io.wide.req_data.bits.data := in_buf >> UFix(((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH - (dbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)*MEM_BACKUP_WIDTH) io.wide.req_data.bits.data := in_buf >> UFix(((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH - (dbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)*MEM_BACKUP_WIDTH)
val dataq = (new queue(REFILL_CYCLES)) { new MemResp } val dataq = (new Queue(REFILL_CYCLES)) { new MemResp }
dataq.io.enq <> io.wide.resp dataq.io.enq <> io.wide.resp
dataq.io.deq.ready := recv_cnt === UFix((rbits-1)/MEM_BACKUP_WIDTH) dataq.io.deq.ready := recv_cnt === UFix((rbits-1)/MEM_BACKUP_WIDTH)

4
uncore/slowio.scala
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@ -28,12 +28,12 @@ class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T)
val out_slow_val = Reg(resetVal = Bool(false)) val out_slow_val = Reg(resetVal = Bool(false))
val out_slow_bits = Reg() { data } val out_slow_bits = Reg() { data }
val fromhost_q = new queue(1)(data) val fromhost_q = new Queue(1)(data)
fromhost_q.io.enq.valid := in_en && (io.in_slow.valid && in_slow_rdy || reset) fromhost_q.io.enq.valid := in_en && (io.in_slow.valid && in_slow_rdy || reset)
fromhost_q.io.enq.bits := io.in_slow.bits fromhost_q.io.enq.bits := io.in_slow.bits
fromhost_q.io.deq <> io.in_fast fromhost_q.io.deq <> io.in_fast
val tohost_q = new queue(1)(data) val tohost_q = new Queue(1)(data)
tohost_q.io.enq <> io.out_fast tohost_q.io.enq <> io.out_fast
tohost_q.io.deq.ready := in_en && io.out_slow.ready && out_slow_val tohost_q.io.deq.ready := in_en && io.out_slow.ready && out_slow_val

4
uncore/uncore.scala
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@ -336,8 +336,8 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
} }
} }
val p_rep_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY val p_rep_data_dep_list = List.fill(ntiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
val x_init_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY val x_init_data_dep_list = List.fill(ntiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
// Free finished transactions // Free finished transactions
for( j <- 0 until ntiles ) { for( j <- 0 until ntiles ) {