diff --git a/uncore/llc.scala b/uncore/llc.scala
index 64d48ce8..a2a5d361 100644
--- a/uncore/llc.scala
+++ b/uncore/llc.scala
@@ -245,7 +245,7 @@ class LLCData(latency: Int, sets: Int, ways: Int, leaf: Mem[Bits]) extends Compo
     val isWriteback = Bool()
     override def clone = new QEntry().asInstanceOf[this.type]
   }
-  val q = (new queue(latency+2)) { new QEntry }
+  val q = (new Queue(latency+2)) { new QEntry }
   val qReady = q.io.count <= UFix(q.entries-latency-1)
   val valid = Reg(resetVal = Bool(false))
   val req = Reg() { io.req.bits.clone }
diff --git a/uncore/memserdes.scala b/uncore/memserdes.scala
index e20f1ec3..cdd109c2 100644
--- a/uncore/memserdes.scala
+++ b/uncore/memserdes.scala
@@ -149,7 +149,7 @@ class MemDessert extends Component // test rig side
   io.wide.req_data.valid := state === s_data
   io.wide.req_data.bits.data := in_buf >> UFix(((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH - (dbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)*MEM_BACKUP_WIDTH)
 
-  val dataq = (new queue(REFILL_CYCLES)) { new MemResp }
+  val dataq = (new Queue(REFILL_CYCLES)) { new MemResp }
   dataq.io.enq <> io.wide.resp
   dataq.io.deq.ready := recv_cnt === UFix((rbits-1)/MEM_BACKUP_WIDTH)
 
diff --git a/uncore/slowio.scala b/uncore/slowio.scala
index 6cf5a3d9..068e90c5 100644
--- a/uncore/slowio.scala
+++ b/uncore/slowio.scala
@@ -28,12 +28,12 @@ class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T)
   val out_slow_val = Reg(resetVal = Bool(false))
   val out_slow_bits = Reg() { data }
 
-  val fromhost_q = new queue(1)(data)
+  val fromhost_q = new Queue(1)(data)
   fromhost_q.io.enq.valid := in_en && (io.in_slow.valid && in_slow_rdy || reset)
   fromhost_q.io.enq.bits := io.in_slow.bits
   fromhost_q.io.deq <> io.in_fast
 
-  val tohost_q = new queue(1)(data)
+  val tohost_q = new Queue(1)(data)
   tohost_q.io.enq <> io.out_fast
   tohost_q.io.deq.ready := in_en && io.out_slow.ready && out_slow_val
 
diff --git a/uncore/uncore.scala b/uncore/uncore.scala
index a1726242..7ffef155 100644
--- a/uncore/uncore.scala
+++ b/uncore/uncore.scala
@@ -336,8 +336,8 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
     }
   }
 
-  val p_rep_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
-  val x_init_data_dep_list = List.fill(ntiles)((new queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
+  val p_rep_data_dep_list = List.fill(ntiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY
+  val x_init_data_dep_list = List.fill(ntiles)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY
 
   // Free finished transactions
   for( j <- 0 until ntiles ) {