Merge pull request #745 from freechipsproject/tile-xbar

Tile xbar

src/main/scala/coreplex/Configs.scala

@@ -163,7 +163,8 @@ class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
 })
 
 class WithRoccExample extends Config((site, here, up) => {
-  case BuildRoCC => Seq(
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(rocc = Seq(
       RoCCParams(
         opcodes = OpcodeSet.custom0,
         generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
@@ -173,8 +174,9 @@ class WithRoccExample extends Config((site, here, up) => {
          nPTWPorts = 1),
       RoCCParams(
          opcodes = OpcodeSet.custom2,
-      generator = (p: Parameters) => Module(new CharacterCountExample()(p))))
-
+         generator = (p: Parameters) => Module(new CharacterCountExample()(p)))
+    ))
+  }
   case RoccMaxTaggedMemXacts => 1
 })
 
@@ -224,3 +226,4 @@ class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, he
 class WithRationalRocketTiles extends Config((site, here, up) => {
   case RocketCrossing => RationalCrossing()
 })
+

src/main/scala/rocket/Frontend.scala

@@ -183,7 +183,7 @@ trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
   val module: HasICacheFrontendModule
   val frontend = LazyModule(new Frontend(hartid: Int))
   val hartid: Int
-  masterNode := frontend.masterNode
+  tileBus.node := frontend.masterNode
   nPTWPorts += 1
 }
 

src/main/scala/rocket/HellaCache.scala

@@ -196,7 +196,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
   def findScratchpadFromICache: Option[AddressSet]
   var nDCachePorts = 0
   val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
-  masterNode := dcache.node
+  tileBus.node := dcache.node
 }
 
 trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle {

src/main/scala/tile/BaseTile.scala

@@ -55,6 +55,8 @@ trait HasTileLinkMasterPort {
   implicit val p: Parameters
   val module: HasTileLinkMasterPortModule
   val masterNode = TLOutputNode()
+  val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
+  masterNode := tileBus.node
 }
 
 trait HasTileLinkMasterPortBundle {

src/main/scala/tile/LegacyRoCC.scala

@@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi
     }})))
 
   legacyRocc foreach { lr =>
-    masterNode := lr.masterNode
+    tileBus.node :=* lr.masterNode
     nPTWPorts += lr.nPTWPorts
     nDCachePorts += lr.nRocc
   }
@@ -66,7 +66,7 @@ trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule
       None
     } foreach { lr =>
       fpu.io.cp_req <> lr.module.io.fpu.cp_req
-      fpu.io.cp_resp <> lr.module.io.fpu.cp_resp
+      lr.module.io.fpu.cp_resp <> fpu.io.cp_resp
     }
   }