From a19fc2549e650cbbc9661f26dc089fabb34322c3 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 16 May 2017 16:12:01 -0700 Subject: [PATCH 1/3] tile: add tileBus xbar --- src/main/scala/rocket/Frontend.scala | 2 +- src/main/scala/rocket/HellaCache.scala | 2 +- src/main/scala/rocket/{Tile.scala => RocketTiles.scala} | 0 src/main/scala/tile/BaseTile.scala | 2 ++ src/main/scala/tile/LegacyRoCC.scala | 2 +- 5 files changed, 5 insertions(+), 3 deletions(-) rename src/main/scala/rocket/{Tile.scala => RocketTiles.scala} (100%) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index c906b21e..94ef4654 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -183,7 +183,7 @@ trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort { val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(hartid: Int)) val hartid: Int - masterNode := frontend.masterNode + tileBus.node := frontend.masterNode nPTWPorts += 1 } diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 0624fe5d..6b3ce443 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -196,7 +196,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters { def findScratchpadFromICache: Option[AddressSet] var nDCachePorts = 0 val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _) - masterNode := dcache.node + tileBus.node := dcache.node } trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle { diff --git a/src/main/scala/rocket/Tile.scala b/src/main/scala/rocket/RocketTiles.scala similarity index 100% rename from src/main/scala/rocket/Tile.scala rename to src/main/scala/rocket/RocketTiles.scala diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 3aef5be2..65f1ad2f 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -55,6 +55,8 @@ trait HasTileLinkMasterPort { implicit val p: Parameters val module: HasTileLinkMasterPortModule val masterNode = TLOutputNode() + val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to + masterNode := tileBus.node } trait HasTileLinkMasterPortBundle { diff --git a/src/main/scala/tile/LegacyRoCC.scala b/src/main/scala/tile/LegacyRoCC.scala index 70b5f89a..7d052021 100644 --- a/src/main/scala/tile/LegacyRoCC.scala +++ b/src/main/scala/tile/LegacyRoCC.scala @@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi }}))) legacyRocc foreach { lr => - masterNode := lr.masterNode + tileBus.node := lr.masterNode nPTWPorts += lr.nPTWPorts nDCachePorts += lr.nRocc } From 5f22e91a7fc828f7b2e552a7b6aebe2bfc0ec822 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 16 May 2017 16:44:53 -0700 Subject: [PATCH 2/3] rocc: fix RoccExampleConfig --- src/main/scala/coreplex/Configs.scala | 26 ++++++++++++++------------ src/main/scala/tile/LegacyRoCC.scala | 4 ++-- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 3a72cb94..7f4f0f16 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -163,18 +163,20 @@ class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => { }) class WithRoccExample extends Config((site, here, up) => { - case BuildRoCC => Seq( - RoCCParams( - opcodes = OpcodeSet.custom0, - generator = (p: Parameters) => Module(new AccumulatorExample()(p))), - RoCCParams( - opcodes = OpcodeSet.custom1, - generator = (p: Parameters) => Module(new TranslatorExample()(p)), - nPTWPorts = 1), - RoCCParams( - opcodes = OpcodeSet.custom2, - generator = (p: Parameters) => Module(new CharacterCountExample()(p)))) - + case RocketTilesKey => up(RocketTilesKey, site) map { r => + r.copy(rocc = Seq( + RoCCParams( + opcodes = OpcodeSet.custom0, + generator = (p: Parameters) => Module(new AccumulatorExample()(p))), + RoCCParams( + opcodes = OpcodeSet.custom1, + generator = (p: Parameters) => Module(new TranslatorExample()(p)), + nPTWPorts = 1), + RoCCParams( + opcodes = OpcodeSet.custom2, + generator = (p: Parameters) => Module(new CharacterCountExample()(p))) + )) + } case RoccMaxTaggedMemXacts => 1 }) diff --git a/src/main/scala/tile/LegacyRoCC.scala b/src/main/scala/tile/LegacyRoCC.scala index 7d052021..52b99082 100644 --- a/src/main/scala/tile/LegacyRoCC.scala +++ b/src/main/scala/tile/LegacyRoCC.scala @@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi }}))) legacyRocc foreach { lr => - tileBus.node := lr.masterNode + tileBus.node :=* lr.masterNode nPTWPorts += lr.nPTWPorts nDCachePorts += lr.nRocc } @@ -66,7 +66,7 @@ trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule None } foreach { lr => fpu.io.cp_req <> lr.module.io.fpu.cp_req - fpu.io.cp_resp <> lr.module.io.fpu.cp_resp + lr.module.io.fpu.cp_resp <> fpu.io.cp_resp } } From d8996ea85f234e339836aac987df352000974663 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 16 May 2017 22:56:58 -0700 Subject: [PATCH 3/3] Empty commit to force travis --- src/main/scala/coreplex/Configs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 7f4f0f16..3a3bb958 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -226,3 +226,4 @@ class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, he class WithRationalRocketTiles extends Config((site, here, up) => { case RocketCrossing => RationalCrossing() }) +