riscv/rocket-chip
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Merge pull request #745 from freechipsproject/tile-xbar

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Tile xbar
This commit is contained in:
Wesley W. Terpstra 2017-05-17 06:28:37 -07:00 committed by GitHub
commit 65053978dc
6 changed files with 21 additions and 16 deletions
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9
src/main/scala/coreplex/Configs.scala
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@ -163,7 +163,8 @@ class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => {
}) })
class WithRoccExample extends Config((site, here, up) => { class WithRoccExample extends Config((site, here, up) => {
case BuildRoCC => Seq( case RocketTilesKey => up(RocketTilesKey, site) map { r =>
r.copy(rocc = Seq(
RoCCParams( RoCCParams(
opcodes = OpcodeSet.custom0, opcodes = OpcodeSet.custom0,
generator = (p: Parameters) => Module(new AccumulatorExample()(p))), generator = (p: Parameters) => Module(new AccumulatorExample()(p))),
@ -173,8 +174,9 @@ class WithRoccExample extends Config((site, here, up) => {
nPTWPorts = 1), nPTWPorts = 1),
RoCCParams( RoCCParams(
opcodes = OpcodeSet.custom2, opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new CharacterCountExample()(p)))) generator = (p: Parameters) => Module(new CharacterCountExample()(p)))
))
}
case RoccMaxTaggedMemXacts => 1 case RoccMaxTaggedMemXacts => 1
}) })
@ -224,3 +226,4 @@ class WithAynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, he
class WithRationalRocketTiles extends Config((site, here, up) => { class WithRationalRocketTiles extends Config((site, here, up) => {
case RocketCrossing => RationalCrossing() case RocketCrossing => RationalCrossing()
}) })

2
src/main/scala/rocket/Frontend.scala
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@ -183,7 +183,7 @@ trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
val module: HasICacheFrontendModule val module: HasICacheFrontendModule
val frontend = LazyModule(new Frontend(hartid: Int)) val frontend = LazyModule(new Frontend(hartid: Int))
val hartid: Int val hartid: Int
masterNode := frontend.masterNode tileBus.node := frontend.masterNode
nPTWPorts += 1 nPTWPorts += 1
} }

2
src/main/scala/rocket/HellaCache.scala
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@ -196,7 +196,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
def findScratchpadFromICache: Option[AddressSet] def findScratchpadFromICache: Option[AddressSet]
var nDCachePorts = 0 var nDCachePorts = 0
val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _) val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
masterNode := dcache.node tileBus.node := dcache.node
} }
trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle { trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle {

0
src/main/scala/rocket/Tile.scala → src/main/scala/rocket/RocketTiles.scala
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2
src/main/scala/tile/BaseTile.scala
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@ -55,6 +55,8 @@ trait HasTileLinkMasterPort {
implicit val p: Parameters implicit val p: Parameters
val module: HasTileLinkMasterPortModule val module: HasTileLinkMasterPortModule
val masterNode = TLOutputNode() val masterNode = TLOutputNode()
val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
masterNode := tileBus.node
} }
trait HasTileLinkMasterPortBundle { trait HasTileLinkMasterPortBundle {

4
src/main/scala/tile/LegacyRoCC.scala
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@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi
}}))) }})))
legacyRocc foreach { lr => legacyRocc foreach { lr =>
masterNode := lr.masterNode tileBus.node :=* lr.masterNode
nPTWPorts += lr.nPTWPorts nPTWPorts += lr.nPTWPorts
nDCachePorts += lr.nRocc nDCachePorts += lr.nRocc
} }
@ -66,7 +66,7 @@ trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule
None None
} foreach { lr => } foreach { lr =>
fpu.io.cp_req <> lr.module.io.fpu.cp_req fpu.io.cp_req <> lr.module.io.fpu.cp_req
fpu.io.cp_resp <> lr.module.io.fpu.cp_resp lr.module.io.fpu.cp_resp <> fpu.io.cp_resp
} }
} }