riscv/rocket-chip
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use named constants to set AXI resp, cache, and prot fields

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This commit is contained in:
Howard Mao
2016-09-13 10:47:36 -07:00
parent f95b8c4ec2
commit 646527c88e
5 changed files with 29 additions and 15 deletions
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5
src/main/scala/rocketchip/Periphery.scala
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@ -5,6 +5,7 @@ package rocketchip
import Chisel._
import cde.{Parameters, Field}
import junctions._
import junctions.NastiConstants._
import uncore.tilelink._
import uncore.tilelink2.{LazyModule, LazyModuleImp}
import uncore.converters._
@ -165,8 +166,8 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
// Abuse the fact that zip takes the shorter of the two lists
((io.mem_axi zip coreplex.io.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
val axi_sync = PeripheryUtils.convertTLtoAXI(mem)(outermostParams)
axi_sync.ar.bits.cache := UInt("b0011")
axi_sync.aw.bits.cache := UInt("b0011")
axi_sync.ar.bits.cache := CACHE_NORMAL_NOCACHE_BUF
axi_sync.aw.bits.cache := CACHE_NORMAL_NOCACHE_BUF
axi <> (
if (!p(AsyncMemChannels)) axi_sync
else AsyncNastiTo(io.mem_clk.get(idx), io.mem_rst.get(idx), axi_sync)