diff --git a/src/main/scala/junctions/nasti.scala b/src/main/scala/junctions/nasti.scala
index 48cd4fb5..ab580523 100644
--- a/src/main/scala/junctions/nasti.scala
+++ b/src/main/scala/junctions/nasti.scala
@@ -135,6 +135,17 @@ object NastiConstants {
   val RESP_EXOKAY = UInt("b01")
   val RESP_SLVERR = UInt("b10")
   val RESP_DECERR = UInt("b11")
+
+  val CACHE_DEVICE_NOBUF = UInt("b0000")
+  val CACHE_DEVICE_BUF   = UInt("b0001")
+  val CACHE_NORMAL_NOCACHE_NOBUF = UInt("b0010")
+  val CACHE_NORMAL_NOCACHE_BUF   = UInt("b0011")
+
+  def AXPROT(instruction: Bool, nonsecure: Bool, privileged: Bool): UInt =
+    Cat(instruction, nonsecure, privileged)
+
+  def AXPROT(instruction: Boolean, nonsecure: Boolean, privileged: Boolean): UInt =
+    AXPROT(Bool(instruction), Bool(nonsecure), Bool(privileged))
 }
 
 import NastiConstants._
@@ -150,8 +161,8 @@ object NastiWriteAddressChannel {
     aw.size := size
     aw.burst := burst
     aw.lock := Bool(false)
-    aw.cache := UInt("b0000")
-    aw.prot := UInt("b000")
+    aw.cache := CACHE_DEVICE_NOBUF
+    aw.prot := AXPROT(false, false, false)
     aw.qos := UInt("b0000")
     aw.region := UInt("b0000")
     aw.user := UInt(0)
@@ -170,8 +181,8 @@ object NastiReadAddressChannel {
     ar.size := size
     ar.burst := burst
     ar.lock := Bool(false)
-    ar.cache := UInt(0)
-    ar.prot := UInt(0)
+    ar.cache := CACHE_DEVICE_NOBUF
+    ar.prot := AXPROT(false, false, false)
     ar.qos := UInt(0)
     ar.region := UInt(0)
     ar.user := UInt(0)
@@ -255,7 +266,7 @@ class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit p: Parameters) e
 
   io.nasti.b.valid := id_q.io.deq.valid && b_ok
   io.nasti.b.bits.id := id_q.io.deq.bits
-  io.nasti.b.bits.resp := UInt(0)
+  io.nasti.b.bits.resp := RESP_OKAY
 
   io.nasti.w.ready := io.mem.req_data.ready
   io.mem.req_data.valid := io.nasti.w.valid
@@ -266,7 +277,7 @@ class MemIONastiIOConverter(cacheBlockOffsetBits: Int)(implicit p: Parameters) e
   io.nasti.r.bits.data := io.mem.resp.bits.data
   io.nasti.r.bits.last := mif_wrap_out
   io.nasti.r.bits.id := io.mem.resp.bits.tag
-  io.nasti.r.bits.resp := UInt(0)
+  io.nasti.r.bits.resp := RESP_OKAY
   io.mem.resp.ready := io.nasti.r.ready
 }
 
@@ -389,7 +400,7 @@ class NastiErrorSlave(implicit p: Parameters) extends NastiModule {
   io.aw.ready := b_queue.io.enq.ready && !draining
   io.b.valid := b_queue.io.deq.valid && !draining
   io.b.bits.id := b_queue.io.deq.bits
-  io.b.bits.resp := Bits("b11")
+  io.b.bits.resp := RESP_DECERR
   b_queue.io.deq.ready := io.b.ready && !draining
 }
 
diff --git a/src/main/scala/junctions/stream.scala b/src/main/scala/junctions/stream.scala
index a9e01af8..24f9ad58 100644
--- a/src/main/scala/junctions/stream.scala
+++ b/src/main/scala/junctions/stream.scala
@@ -45,7 +45,7 @@ class NastiIOStreamIOConverter(w: Int)(implicit p: Parameters) extends Module {
   io.nasti.ar.ready := !reading
   io.nasti.r.valid := reading && io.stream.in.valid
   io.nasti.r.bits := io.stream.in.bits
-  io.nasti.r.bits.resp := UInt(0)
+  io.nasti.r.bits.resp := RESP_OKAY
   io.nasti.r.bits.id := read_id
   io.stream.in.ready := reading && io.nasti.r.ready
 
@@ -72,7 +72,7 @@ class NastiIOStreamIOConverter(w: Int)(implicit p: Parameters) extends Module {
   io.stream.out.valid := writing && io.nasti.w.valid
   io.stream.out.bits := io.nasti.w.bits
   io.nasti.b.valid := write_resp
-  io.nasti.b.bits.resp := UInt(0)
+  io.nasti.b.bits.resp := RESP_OKAY
   io.nasti.b.bits.id := write_id
 
   when (io.nasti.aw.fire()) {
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 30b5fd32..cc0f36ca 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -5,6 +5,7 @@ package rocketchip
 import Chisel._
 import cde.{Parameters, Field}
 import junctions._
+import junctions.NastiConstants._
 import uncore.tilelink._
 import uncore.tilelink2.{LazyModule, LazyModuleImp}
 import uncore.converters._
@@ -165,8 +166,8 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
   // Abuse the fact that zip takes the shorter of the two lists
   ((io.mem_axi zip coreplex.io.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
     val axi_sync = PeripheryUtils.convertTLtoAXI(mem)(outermostParams)
-    axi_sync.ar.bits.cache := UInt("b0011")
-    axi_sync.aw.bits.cache := UInt("b0011")
+    axi_sync.ar.bits.cache := CACHE_NORMAL_NOCACHE_BUF
+    axi_sync.aw.bits.cache := CACHE_NORMAL_NOCACHE_BUF
     axi <> (
       if (!p(AsyncMemChannels)) axi_sync
       else AsyncNastiTo(io.mem_clk.get(idx), io.mem_rst.get(idx), axi_sync)
diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index 15fe6c7c..0fdc8a30 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -6,6 +6,7 @@ import Chisel._
 import cde.{Parameters, Field}
 import rocket.Util._
 import junctions._
+import junctions.NastiConstants._
 
 case object BuildExampleTop extends Field[Parameters => ExampleTop]
 case object SimMemLatency extends Field[Int]
@@ -117,12 +118,12 @@ class SimAXIMem(size: BigInt)(implicit p: Parameters) extends NastiModule()(p) {
 
   io.axi.b.valid := bValid
   io.axi.b.bits.id := aw.id
-  io.axi.b.bits.resp := UInt(0)
+  io.axi.b.bits.resp := RESP_OKAY
 
   io.axi.r.valid := rValid
   io.axi.r.bits.id := ar.id
   io.axi.r.bits.data := mem((ar.addr >> log2Ceil(nastiXDataBits/8))(log2Ceil(depth)-1, 0))
-  io.axi.r.bits.resp := UInt(0)
+  io.axi.r.bits.resp := RESP_OKAY
   io.axi.r.bits.last := ar.len === UInt(0)
 }
 
diff --git a/src/main/scala/uncore/converters/Nasti.scala b/src/main/scala/uncore/converters/Nasti.scala
index 0743b488..3477e976 100644
--- a/src/main/scala/uncore/converters/Nasti.scala
+++ b/src/main/scala/uncore/converters/Nasti.scala
@@ -3,6 +3,7 @@ package uncore.converters
 import Chisel._
 import junctions._
 import util.{ReorderQueue, DecoupledHelper}
+import junctions.NastiConstants._
 import uncore.tilelink._
 import uncore.constants._
 import cde.Parameters
@@ -234,8 +235,8 @@ class NastiIOTileLinkIOConverter(implicit p: Parameters) extends TLModule()(p)
     data = Bits(0))
   assert(!gnt_arb.io.in(1).valid || put_id_mapper.io.resp.matches, "NASTI tag error")
 
-  assert(!io.nasti.r.valid || io.nasti.r.bits.resp === UInt(0), "NASTI read error")
-  assert(!io.nasti.b.valid || io.nasti.b.bits.resp === UInt(0), "NASTI write error")
+  assert(!io.nasti.r.valid || io.nasti.r.bits.resp === RESP_OKAY, "NASTI read error")
+  assert(!io.nasti.b.valid || io.nasti.b.bits.resp === RESP_OKAY, "NASTI write error")
 }
 
 class TileLinkIONastiIOConverter(implicit p: Parameters) extends TLModule()(p)