Add BusErrorUnit RegFieldDesc
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@ -68,17 +68,17 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
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io.interrupt := (accrued.asUInt & local_interrupt.asUInt).orR
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int_out(0) := (accrued.asUInt & global_interrupt.asUInt).orR
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def reg(r: UInt) = RegField.bytes(r, (r.getWidth + 7)/8)
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def reg(v: Vec[Bool]) = v.map(r => RegField(1, r))
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def reg(r: UInt, name: String, reset: Option[BigInt]) = RegFieldGroup(name, None, RegField.bytes(r, (r.getWidth + 7)/8, Some(RegFieldDesc(name, "", reset=reset))))
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def reg(v: Vec[Bool], name: String, reset: Option[BigInt]) = RegFieldGroup(name, None, v.map(r => RegField(1, r, RegFieldDesc(name, "", reset=reset))))
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def numberRegs(x: Seq[Seq[RegField]]) = x.zipWithIndex.map { case (f, i) => (i * regWidth / 8) -> f }
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node.regmap(numberRegs(Seq(
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reg(cause),
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reg(value),
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reg(enable),
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reg(global_interrupt),
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reg(accrued),
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reg(local_interrupt))):_*)
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reg(cause, "cause", Some(BigInt(0))),
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reg(value, "value", None),
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reg(enable, "enable", Some(sources.zipWithIndex.map { case (s, i) => BigInt(s.size) << i }.sum)),
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reg(global_interrupt, "plic_interrupt", Some(BigInt(0))),
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reg(accrued, "accrued", Some(BigInt(0))),
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reg(local_interrupt, "local_interrupt", Some(BigInt(0))))):_*)
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// hardwire mask bits for unsupported sources to 0
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for ((s, i) <- sources.zipWithIndex; if s.isEmpty) {
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