riscv/rocket-chip
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Expose BusErrorUnit non-diplomatically for use as local interrupt

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This commit is contained in:
Andrew Waterman 2017-11-06 16:39:02 -08:00
parent bdda2cb145
commit 6357db0b12
1 changed files with 3 additions and 1 deletions
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4
src/main/scala/rocket/BusErrorUnit.scala
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@ -40,6 +40,7 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle { val io = IO(new Bundle {
val errors = t.flip val errors = t.flip
val interrupt = Bool().asOutput
}) })
val sources = io.errors.toErrorList val sources = io.errors.toErrorList
@ -61,7 +62,8 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
} }
val (int_out, _) = intNode.out(0) val (int_out, _) = intNode.out(0)
int_out(0) := (accrued & interrupt).orR io.interrupt := (accrued & interrupt).orR
int_out(0) := io.interrupt
def reg(r: UInt) = RegField(regWidth, r) def reg(r: UInt) = RegField(regWidth, r)
def maskedReg(r: UInt, m: UInt) = RegField(regWidth, r, RegWriteFn((v, d) => { when (v) { r := d & m }; true })) def maskedReg(r: UInt, m: UInt) = RegField(regWidth, r, RegWriteFn((v, d) => { when (v) { r := d & m }; true }))