From 6357db0b1234be00832e374e7768c5f7f9c17262 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 6 Nov 2017 16:39:02 -0800 Subject: [PATCH] Expose BusErrorUnit non-diplomatically for use as local interrupt --- src/main/scala/rocket/BusErrorUnit.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/BusErrorUnit.scala b/src/main/scala/rocket/BusErrorUnit.scala index d3928fee..b2b95d2a 100644 --- a/src/main/scala/rocket/BusErrorUnit.scala +++ b/src/main/scala/rocket/BusErrorUnit.scala @@ -40,6 +40,7 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit lazy val module = new LazyModuleImp(this) { val io = IO(new Bundle { val errors = t.flip + val interrupt = Bool().asOutput }) val sources = io.errors.toErrorList @@ -61,7 +62,8 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit } val (int_out, _) = intNode.out(0) - int_out(0) := (accrued & interrupt).orR + io.interrupt := (accrued & interrupt).orR + int_out(0) := io.interrupt def reg(r: UInt) = RegField(regWidth, r) def maskedReg(r: UInt, m: UInt) = RegField(regWidth, r, RegWriteFn((v, d) => { when (v) { r := d & m }; true }))