riscv/rocket-chip
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Make PRCI a singleton, not per-tile

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Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
This commit is contained in:
Andrew Waterman 2016-06-05 23:06:21 -07:00
parent be7500e4a9
commit 631e3e2dd9
1 changed files with 27 additions and 15 deletions
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42
uncore/src/main/scala/prci.scala
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@ -25,27 +25,29 @@ class PRCITileIO(implicit p: Parameters) extends Bundle {
override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type] override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type]
} }
/** Power, Reset, Clock, Interrupt */
class PRCI(implicit val p: Parameters) extends Module class PRCI(implicit val p: Parameters) extends Module
with HasTileLinkParameters with HasTileLinkParameters
with HasAddrMapParameters { with HasAddrMapParameters {
val io = new Bundle { val io = new Bundle {
val id = UInt(INPUT, log2Up(p(NTiles))) val interrupts = Vec(p(NTiles), new Bundle {
val interrupts = new Bundle {
val mtip = Bool() val mtip = Bool()
val meip = Bool() val meip = Bool()
val seip = Bool() val seip = Bool()
val debug = Bool() val debug = Bool()
}.asInput }).asInput
val tl = new ClientUncachedTileLinkIO().flip val tl = new ClientUncachedTileLinkIO().flip
val tile = new PRCITileIO val tiles = Vec(p(NTiles), new PRCITileIO)
} }
val ipi = Reg(init=Bool(false)) val ipi = Reg(init=Vec.fill(p(NTiles))(Bool(false)))
val acq = Queue(io.tl.acquire, 1) val acq = Queue(io.tl.acquire, 1)
val addr = acq.bits.full_addr()
val read = acq.bits.isBuiltInType(Acquire.getType) val read = acq.bits.isBuiltInType(Acquire.getType)
val write = acq.bits.isBuiltInType(Acquire.putType) val write = acq.bits.isBuiltInType(Acquire.putType)
val rdata = Wire(init=ipi) val rdata = Wire(init=UInt(0))
val masked_wdata = (acq.bits.data & acq.bits.full_wmask()) | (rdata & ~acq.bits.full_wmask())
io.tl.grant.valid := acq.valid io.tl.grant.valid := acq.valid
acq.ready := io.tl.grant.ready acq.ready := io.tl.grant.ready
io.tl.grant.bits := Grant( io.tl.grant.bits := Grant(
@ -56,15 +58,25 @@ class PRCI(implicit val p: Parameters) extends Module
addr_beat = UInt(0), addr_beat = UInt(0),
data = rdata) data = rdata)
val regSize = 16 when (write) {
val nRegs = 2 val ipiRegBytes = 4
val addr = acq.bits.full_addr()(log2Up(regSize*nRegs)-1,log2Up(regSize)) val regsPerBeat = tlDataBytes/ipiRegBytes
val word =
when (addr === UInt(0) && write) { if (regsPerBeat >= ipi.size) UInt(0)
ipi := acq.bits.data(0) else addr(log2Up(ipi.size*ipiRegBytes)-1,log2Up(tlDataBytes))
for (i <- 0 until ipi.size by regsPerBeat) {
when (word === i/regsPerBeat) {
rdata := Cat(ipi.slice(i, i + regsPerBeat).map(p => Cat(UInt(0, 8*ipiRegBytes-1), p)).reverse)
for (j <- 0 until (regsPerBeat min (ipi.size - i))) {
when (write) { ipi(i+j) := masked_wdata(j*8*ipiRegBytes) }
}
}
}
} }
io.tile.interrupts := io.interrupts for ((tile, i) <- io.tiles zipWithIndex) {
io.tile.interrupts.msip := ipi tile.interrupts := io.interrupts(i)
io.tile.id := io.id tile.interrupts.msip := ipi(i)
tile.id := UInt(i)
}
} }