hookup vitlb ptw port

2012-03-17 23:00:51 -07:00
parent b793d63182
commit 62ada5ea9e
2 changed files with 32 additions and 18 deletions
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@ -100,6 +100,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
  // and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
  ptw.io.dtlb             <> dtlb.io.ptw;
  ptw.io.itlb             <> itlb.io.ptw;
+  ptw.io.vitlb            <> vitlb.io.ptw
  ptw.io.ptbr             := dpath.io.ptbr;
  arb.io.requestor(DMEM_PTW) <> ptw.io.dmem
  arb.io.dmem             <> io.dmem