riscv/rocket-chip
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debug: Put DebugROM back inside the overall Debug Module (#647)

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Megan Wachs authored and GitHub committed 2017-04-03 16:36:53 -07:00
1 parent d2c1bdc2ce
commit 629e9a2ef6
3 files changed
+4 -20
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src/main/scala/coreplex/RISCVPlatform.scala
-2
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@@ -15,12 +15,10 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
val module: CoreplexRISCVPlatformModule
val debug = LazyModule(new TLDebugModule())
val debug_rom = LazyModule(new TLDebugModuleROM())
val plic = LazyModule(new TLPLIC(maxPriorities = 7))
val clint = LazyModule(new CoreplexLocalInterrupter)
debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
debug_rom.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)