riscv/rocket-chip
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fix HellaQueue deq.valid signal

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This commit is contained in:
Andrew Waterman 2013-01-28 20:57:43 -08:00
parent 45d8066f45
commit 6275e009f8
1 changed files with 3 additions and 1 deletions
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4
rocket/src/main/scala/util.scala
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@ -95,8 +95,10 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Component
val ram = Mem(entries, seqRead = true){data} val ram = Mem(entries, seqRead = true){data}
val ram_out = Reg{data} val ram_out = Reg{data}
val ram_out_valid = Reg(io.deq.ready) val ram_out_valid = Reg{Bool()}
ram_out_valid := Bool(false)
when (io.deq.ready && !empty) { when (io.deq.ready && !empty) {
ram_out_valid := Bool(true)
ram_out := ram(Mux(io.deq.valid, deq_ptr + UFix(1), deq_ptr)) ram_out := ram(Mux(io.deq.valid, deq_ptr + UFix(1), deq_ptr))
} }
when (do_enq) { ram(enq_ptr) := io.enq.bits } when (do_enq) { ram(enq_ptr) := io.enq.bits }