From 6275e009f8461108e9abe3296116a7228d4b1bb8 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 28 Jan 2013 20:57:43 -0800 Subject: [PATCH] fix HellaQueue deq.valid signal --- rocket/src/main/scala/util.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 2e99d4e4..dc0e49c5 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -95,8 +95,10 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Component val ram = Mem(entries, seqRead = true){data} val ram_out = Reg{data} - val ram_out_valid = Reg(io.deq.ready) + val ram_out_valid = Reg{Bool()} + ram_out_valid := Bool(false) when (io.deq.ready && !empty) { + ram_out_valid := Bool(true) ram_out := ram(Mux(io.deq.valid, deq_ptr + UFix(1), deq_ptr)) } when (do_enq) { ram(enq_ptr) := io.enq.bits }