riscv/rocket-chip
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Make instantiated RoCC use dcacheParams

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This commit is contained in:
Schuyler Eldridge
2016-12-04 19:01:39 -08:00
committed by Henry Cook
parent 9fb7934a37
commit 624db2034b
1 changed files with 3 additions and 3 deletions
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src/main/scala/rocket/tile.scala
+1 -1
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@@ -95,7 +95,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
cmdRouter.io.in <> core.io.rocc.cmd
val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
val rocc = accelParams.generator(p.alterPartial({
val rocc = accelParams.generator(dcacheParams.alterPartial({
case RoccNMemChannels => accelParams.nMemChannels
case RoccNPTWPorts => accelParams.nPTWPorts
}))