From 624db2034b55d889b313383c81f74b1c5190e904 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge <schuyler.eldridge@gmail.com>
Date: Tue, 29 Nov 2016 19:34:26 -0500
Subject: [PATCH] Make instantiated RoCC use dcacheParams

---
 src/main/scala/rocket/tile.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala
index ca134251..ec0e7ff1 100644
--- a/src/main/scala/rocket/tile.scala
+++ b/src/main/scala/rocket/tile.scala
@@ -54,9 +54,9 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
   cachedOut := dcache.node
   uncachedOut := TLHintHandler()(ucLegacy.node)
   val masterNodes = List(cachedOut, uncachedOut)
-  
+
   (slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
-  
+
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
       val cached = cachedOut.bundleOut
@@ -95,7 +95,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
       cmdRouter.io.in <> core.io.rocc.cmd
 
       val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
-        val rocc = accelParams.generator(p.alterPartial({
+        val rocc = accelParams.generator(dcacheParams.alterPartial({
           case RoccNMemChannels => accelParams.nMemChannels
           case RoccNPTWPorts => accelParams.nPTWPorts
         }))