riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Make instantiated RoCC use dcacheParams

Browse Source
This commit is contained in:
Schuyler Eldridge 2016-11-29 19:34:26 -05:00 committed by Henry Cook
parent 9fb7934a37
commit 624db2034b
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/rocket/tile.scala
View File

@ -54,9 +54,9 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
cachedOut := dcache.node cachedOut := dcache.node
uncachedOut := TLHintHandler()(ucLegacy.node) uncachedOut := TLHintHandler()(ucLegacy.node)
val masterNodes = List(cachedOut, uncachedOut) val masterNodes = List(cachedOut, uncachedOut)
(slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) } (slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = new Bundle { val io = new Bundle {
val cached = cachedOut.bundleOut val cached = cachedOut.bundleOut
@ -95,7 +95,7 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
cmdRouter.io.in <> core.io.rocc.cmd cmdRouter.io.in <> core.io.rocc.cmd
val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) => val roccs = buildRocc.zipWithIndex.map { case (accelParams, i) =>
val rocc = accelParams.generator(p.alterPartial({ val rocc = accelParams.generator(dcacheParams.alterPartial({
case RoccNMemChannels => accelParams.nMemChannels case RoccNMemChannels => accelParams.nMemChannels
case RoccNPTWPorts => accelParams.nPTWPorts case RoccNPTWPorts => accelParams.nPTWPorts
})) }))