riscv/rocket-chip
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more tlb/ptw fixes

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This commit is contained in:
Rimas Avizienis
2011-11-10 00:23:29 -08:00
parent 6664af3bc0
commit 62407b4668
6 changed files with 93 additions and 36 deletions
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52
rocket/src/main/scala/ptw.scala
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@ -32,14 +32,15 @@ class rocketDmemArbiter extends Component
io.ptw.resp_data := io.mem.resp_data;
io.cpu.resp_data := io.mem.resp_data;
io.cpu.resp_tag := io.mem.resp_tag;
// io.cpu.resp_tag := io.mem.resp_tag(11,0);
io.cpu.resp_tag := io.mem.resp_tag; // to get rid of warning, MSB of tag is ignored in dpath
}
class ioPTW extends Bundle
{
val itlb = new ioTLB_PTW().flip();
// val dtlb = new ioTLB_PTW.flip();
val dtlb = new ioTLB_PTW().flip();
val dmem = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_addr", "resp_data", "resp_val")).flip();
val ptbr = UFix(PADDR_BITS, 'input);
}
@ -52,17 +53,31 @@ class rocketPTW extends Component
val state = Reg(resetVal = s_ready);
val r_req_vpn = Reg(resetVal = Bits(0,VPN_BITS));
val r_req_dest = Reg(resetVal = Bool(false)); // 0 = ITLB, 1 = DTLB
val req_addr = Reg(resetVal = UFix(0,PPN_BITS+PGIDX_BITS));
val r_resp_ppn = Reg(resetVal = Bits(0,PPN_BITS));
val r_resp_perm = Reg(resetVal = Bits(0,PERM_BITS));
val vpn_idx = Mux(state === s_l2_wait, r_req_vpn(9,0), r_req_vpn(19,10));
val req_val = io.itlb.req_val || io.dtlb.req_val;
when ((state === s_ready) && io.itlb.req_val) {
// give ITLB requests priority over DTLB requests
val req_itlb_val = io.itlb.req_val;
val req_dtlb_val = io.dtlb.req_val && !io.itlb.req_val;
when ((state === s_ready) && req_itlb_val) {
r_req_vpn <== io.itlb.req_vpn;
r_req_dest <== Bool(false);
req_addr <== Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.itlb.req_vpn(VPN_BITS-1,VPN_BITS-10)).toUFix;
}
when ((state === s_ready) && req_dtlb_val) {
r_req_vpn <== io.dtlb.req_vpn;
r_req_dest <== Bool(true);
req_addr <== Cat(io.ptbr(PADDR_BITS-1,PGIDX_BITS), io.dtlb.req_vpn(VPN_BITS-1,VPN_BITS-10)).toUFix;
}
when (io.dmem.resp_val) {
req_addr <== Cat(io.dmem.resp_data(PADDR_BITS-1, PGIDX_BITS), vpn_idx).toUFix;
r_resp_perm <== io.dmem.resp_data(9,4);
@ -78,22 +93,33 @@ class rocketPTW extends Component
io.dmem.req_type := MT_D;
io.dmem.req_addr := req_addr;
io.itlb.req_rdy := (state === s_ready);
io.itlb.resp_val := (state === s_done) || (state === s_l1_fake) || (state === s_l2_fake);
io.itlb.resp_err := (state === s_error);
io.itlb.resp_perm := r_resp_perm;
io.itlb.resp_ppn :=
Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-11, 0)),
Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-21, 0)),
r_resp_ppn));
val resp_val = (state === s_done) || (state === s_l1_fake) || (state === s_l2_fake);
val resp_err = (state === s_error);
val resp_ptd = (io.dmem.resp_data(1,0) === Bits(1,2));
val resp_pte = (io.dmem.resp_data(1,0) === Bits(2,2));
io.dtlb.req_rdy := (state === s_ready) && !io.itlb.req_val;
io.itlb.req_rdy := (state === s_ready);
io.dtlb.resp_val := r_req_dest && resp_val;
io.itlb.resp_val := !r_req_dest && resp_val;
io.dtlb.resp_err := r_req_dest && resp_err;
io.itlb.resp_err := !r_req_dest && resp_err;
io.dtlb.resp_perm := r_resp_perm;
io.itlb.resp_perm := r_resp_perm;
val resp_ppn =
Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-11, 0)),
Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-21, 0)),
r_resp_ppn));
io.dtlb.resp_ppn := resp_ppn;
io.itlb.resp_ppn := resp_ppn;
// control state machine
switch (state) {
is (s_ready) {
when (io.itlb.req_val) {
when (req_val) {
state <== s_l1_req;
}
}