fix bus axi connections in periphery
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f9ea14b4c2
commit
61aa716f44
@ -129,7 +129,7 @@ class BasePlatformConfig extends Config (
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case ExportMMIOPort => site(ExtraDevices).addrMapEntries.size > 0
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case ExportMMIOPort => site(ExtraDevices).addrMapEntries.size > 0
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case AsyncBusChannels => false
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case NExtBusAXIChannels => 0
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case NExternalClients => (if (site(NExtBusAXIChannels) > 1) 1 else 0) +
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case NExternalClients => (if (site(NExtBusAXIChannels) > 0) 1 else 0) +
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site(ExtraDevices).nClientPorts
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site(ExtraDevices).nClientPorts
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case ConnectExtraPorts =>
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case ConnectExtraPorts =>
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(out: Bundle, in: Bundle, p: Parameters) => out <> in
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(out: Bundle, in: Bundle, p: Parameters) => out <> in
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@ -198,7 +198,7 @@ class Periphery(implicit val p: Parameters) extends Module
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val conv = Module(new TileLinkIONastiIOConverter)
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val conv = Module(new TileLinkIONastiIOConverter)
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val arb = Module(new NastiArbiter(io.bus_axi.size))
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val arb = Module(new NastiArbiter(io.bus_axi.size))
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arb.io.master <> io.bus_axi
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arb.io.master <> io.bus_axi
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conv.io.nasti <> conv.io.tl
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conv.io.nasti <> arb.io.slave
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io.clients_out.head <> conv.io.tl
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io.clients_out.head <> conv.io.tl
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}
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}
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@ -239,6 +239,7 @@ class Periphery(implicit val p: Parameters) extends Module
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deviceMMIO += (entry.name -> mmioNetwork.port(entry.name))
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deviceMMIO += (entry.name -> mmioNetwork.port(entry.name))
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val deviceClients = if (io.bus_axi.size > 0) io.clients_out.tail else io.clients_out
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val deviceClients = if (io.bus_axi.size > 0) io.clients_out.tail else io.clients_out
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require(deviceClients.size == extraDevices.nClientPorts)
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val buildParams = p.alterPartial({
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val buildParams = p.alterPartial({
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case InnerTLId => "L2toMMIO" // Device MMIO port
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case InnerTLId => "L2toMMIO" // Device MMIO port
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@ -20,10 +20,8 @@ class TestHarness(implicit p: Parameters) extends Module {
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require(dut.io.mem_tl.isEmpty)
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require(dut.io.mem_tl.isEmpty)
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require(dut.io.bus_clk.isEmpty)
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require(dut.io.bus_clk.isEmpty)
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require(dut.io.bus_rst.isEmpty)
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require(dut.io.bus_rst.isEmpty)
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require(dut.io.bus_axi.isEmpty)
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require(dut.io.mmio_clk.isEmpty)
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require(dut.io.mmio_clk.isEmpty)
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require(dut.io.mmio_rst.isEmpty)
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require(dut.io.mmio_rst.isEmpty)
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require(dut.io.mmio_axi.isEmpty)
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require(dut.io.mmio_ahb.isEmpty)
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require(dut.io.mmio_ahb.isEmpty)
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require(dut.io.mmio_tl.isEmpty)
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require(dut.io.mmio_tl.isEmpty)
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require(dut.io.debug_clk.isEmpty)
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require(dut.io.debug_clk.isEmpty)
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@ -41,6 +39,19 @@ class TestHarness(implicit p: Parameters) extends Module {
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Module(new SimAXIMem(memSize / dut.io.mem_axi.size)).io.axi <> axi
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Module(new SimAXIMem(memSize / dut.io.mem_axi.size)).io.axi <> axi
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}
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}
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for (bus_axi <- dut.io.bus_axi) {
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bus_axi.ar.valid := Bool(false)
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bus_axi.aw.valid := Bool(false)
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bus_axi.w.valid := Bool(false)
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bus_axi.r.ready := Bool(false)
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bus_axi.b.ready := Bool(false)
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}
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for (mmio_axi <- dut.io.mmio_axi) {
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val slave = Module(new NastiErrorSlave)
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slave.io <> mmio_axi
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}
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val dtm = Module(new SimDTM)
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val dtm = Module(new SimDTM)
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dut.io.debug <> dtm.io.debug
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dut.io.debug <> dtm.io.debug
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dtm.io.clk := clock
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dtm.io.clk := clock
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