From 61aa716f44f0696319eb8440b673554840766a96 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Fri, 19 Aug 2016 18:57:34 -0700
Subject: [PATCH] fix bus axi connections in periphery

---
 src/main/scala/rocketchip/Configs.scala     |  2 +-
 src/main/scala/rocketchip/RocketChip.scala  |  3 ++-
 src/main/scala/rocketchip/TestHarness.scala | 15 +++++++++++++--
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index e91b815e..390605ba 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -129,7 +129,7 @@ class BasePlatformConfig extends Config (
       case ExportMMIOPort => site(ExtraDevices).addrMapEntries.size > 0
       case AsyncBusChannels => false
       case NExtBusAXIChannels => 0
-      case NExternalClients => (if (site(NExtBusAXIChannels) > 1) 1 else 0) +
+      case NExternalClients => (if (site(NExtBusAXIChannels) > 0) 1 else 0) +
                                 site(ExtraDevices).nClientPorts
       case ConnectExtraPorts =>
         (out: Bundle, in: Bundle, p: Parameters) => out <> in
diff --git a/src/main/scala/rocketchip/RocketChip.scala b/src/main/scala/rocketchip/RocketChip.scala
index 6d961c17..60bc2e94 100644
--- a/src/main/scala/rocketchip/RocketChip.scala
+++ b/src/main/scala/rocketchip/RocketChip.scala
@@ -198,7 +198,7 @@ class Periphery(implicit val p: Parameters) extends Module
     val conv = Module(new TileLinkIONastiIOConverter)
     val arb = Module(new NastiArbiter(io.bus_axi.size))
     arb.io.master <> io.bus_axi
-    conv.io.nasti <> conv.io.tl
+    conv.io.nasti <> arb.io.slave
     io.clients_out.head <> conv.io.tl
   }
 
@@ -239,6 +239,7 @@ class Periphery(implicit val p: Parameters) extends Module
       deviceMMIO += (entry.name -> mmioNetwork.port(entry.name))
 
     val deviceClients = if (io.bus_axi.size > 0) io.clients_out.tail else io.clients_out
+    require(deviceClients.size == extraDevices.nClientPorts)
 
     val buildParams = p.alterPartial({
       case InnerTLId => "L2toMMIO" // Device MMIO port
diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala
index c976f4eb..0081ea9d 100644
--- a/src/main/scala/rocketchip/TestHarness.scala
+++ b/src/main/scala/rocketchip/TestHarness.scala
@@ -20,10 +20,8 @@ class TestHarness(implicit p: Parameters) extends Module {
   require(dut.io.mem_tl.isEmpty)
   require(dut.io.bus_clk.isEmpty)
   require(dut.io.bus_rst.isEmpty)
-  require(dut.io.bus_axi.isEmpty)
   require(dut.io.mmio_clk.isEmpty)
   require(dut.io.mmio_rst.isEmpty)
-  require(dut.io.mmio_axi.isEmpty)
   require(dut.io.mmio_ahb.isEmpty)
   require(dut.io.mmio_tl.isEmpty)
   require(dut.io.debug_clk.isEmpty)
@@ -41,6 +39,19 @@ class TestHarness(implicit p: Parameters) extends Module {
       Module(new SimAXIMem(memSize / dut.io.mem_axi.size)).io.axi <> axi
   }
 
+  for (bus_axi <- dut.io.bus_axi) {
+    bus_axi.ar.valid := Bool(false)
+    bus_axi.aw.valid := Bool(false)
+    bus_axi.w.valid  := Bool(false)
+    bus_axi.r.ready  := Bool(false)
+    bus_axi.b.ready  := Bool(false)
+  }
+
+  for (mmio_axi <- dut.io.mmio_axi) {
+    val slave = Module(new NastiErrorSlave)
+    slave.io <> mmio_axi
+  }
+
   val dtm = Module(new SimDTM)
   dut.io.debug <> dtm.io.debug
   dtm.io.clk := clock