riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

fix bus axi connections in periphery

Browse Source
This commit is contained in:
Howard Mao
2016-08-19 18:57:34 -07:00
parent f9ea14b4c2
commit 61aa716f44
3 changed files with 16 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/main/scala/rocketchip/TestHarness.scala
View File

@ -20,10 +20,8 @@ class TestHarness(implicit p: Parameters) extends Module {
require(dut.io.mem_tl.isEmpty)
require(dut.io.bus_clk.isEmpty)
require(dut.io.bus_rst.isEmpty)
require(dut.io.bus_axi.isEmpty)
require(dut.io.mmio_clk.isEmpty)
require(dut.io.mmio_rst.isEmpty)
require(dut.io.mmio_axi.isEmpty)
require(dut.io.mmio_ahb.isEmpty)
require(dut.io.mmio_tl.isEmpty)
require(dut.io.debug_clk.isEmpty)
@ -41,6 +39,19 @@ class TestHarness(implicit p: Parameters) extends Module {
Module(new SimAXIMem(memSize / dut.io.mem_axi.size)).io.axi <> axi
}
for (bus_axi <- dut.io.bus_axi) {
bus_axi.ar.valid := Bool(false)
bus_axi.aw.valid := Bool(false)
bus_axi.w.valid := Bool(false)
bus_axi.r.ready := Bool(false)
bus_axi.b.ready := Bool(false)
}
for (mmio_axi <- dut.io.mmio_axi) {
val slave = Module(new NastiErrorSlave)
slave.io <> mmio_axi
}
val dtm = Module(new SimDTM)
dut.io.debug <> dtm.io.debug
dtm.io.clk := clock