riscv/rocket-chip
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fix bus axi connections in periphery

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Howard Mao
2016-08-19 18:57:34 -07:00
parent f9ea14b4c2
commit 61aa716f44
3 changed files with 16 additions and 4 deletions
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2
src/main/scala/rocketchip/Configs.scala
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@ -129,7 +129,7 @@ class BasePlatformConfig extends Config (
case ExportMMIOPort => site(ExtraDevices).addrMapEntries.size > 0
case AsyncBusChannels => false
case NExtBusAXIChannels => 0
case NExternalClients => (if (site(NExtBusAXIChannels) > 1) 1 else 0) +
case NExternalClients => (if (site(NExtBusAXIChannels) > 0) 1 else 0) +
site(ExtraDevices).nClientPorts
case ConnectExtraPorts =>
(out: Bundle, in: Bundle, p: Parameters) => out <> in