riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Minor D$ code cleanup

Browse Source
This commit is contained in:
Andrew Waterman
2017-06-21 02:19:13 -07:00
parent 9c78ac4d78
commit 6100600179
1 changed files with 2 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/rocket/DCache.scala
View File

@@ -11,7 +11,6 @@ import uncore.tilelink2._
import uncore.util._
import util._
import TLMessages._
import scala.math.min
class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val addr = Bits(width = untagBits)
@@ -74,13 +73,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
case _ => false
}
val tl_out_a = Wire(tl_out.a)
val q_depth = if (rational) min(2, maxUncachedInFlight-1) else 0
if (q_depth <= 0) {
tl_out.a <> tl_out_a
} else {
tl_out.a <> Queue(tl_out_a, q_depth, flow = true, pipe = true)
}
val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0
val tl_out_a = if (q_depth == 0) tl_out.a else Queue(tl_out.a, q_depth, flow = true, pipe = true)
val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false))
val s1_probe = Reg(next=tl_out.b.fire(), init=Bool(false))