From 61006001795700db3b169bf907b7b8ec05959d0e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 21 Jun 2017 02:19:13 -0700 Subject: [PATCH] Minor D$ code cleanup --- src/main/scala/rocket/DCache.scala | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 2200f0e9..accc4998 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -11,7 +11,6 @@ import uncore.tilelink2._ import uncore.util._ import util._ import TLMessages._ -import scala.math.min class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = Bits(width = untagBits) @@ -74,13 +73,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { case _ => false } - val tl_out_a = Wire(tl_out.a) - val q_depth = if (rational) min(2, maxUncachedInFlight-1) else 0 - if (q_depth <= 0) { - tl_out.a <> tl_out_a - } else { - tl_out.a <> Queue(tl_out_a, q_depth, flow = true, pipe = true) - } + val q_depth = if (rational) (2 min maxUncachedInFlight-1) else 0 + val tl_out_a = if (q_depth == 0) tl_out.a else Queue(tl_out.a, q_depth, flow = true, pipe = true) val s1_valid = Reg(next=io.cpu.req.fire(), init=Bool(false)) val s1_probe = Reg(next=tl_out.b.fire(), init=Bool(false))