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ahb: make hreadyout fuzzing a sram parameter

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This commit is contained in:
Henry Cook 2017-04-25 11:10:19 -07:00
parent ca435c2f40
commit 60d71efa36
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/uncore/ahb/SRAM.scala
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@ -7,7 +7,7 @@ import config._
import diplomacy._ import diplomacy._
import util._ import util._
class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, fuzzHreadyout: Boolean = false)(implicit p: Parameters) extends LazyModule
{ {
val node = AHBSlaveNode(Seq(AHBSlavePortParameters( val node = AHBSlaveNode(Seq(AHBSlavePortParameters(
Seq(AHBSlaveParameters( Seq(AHBSlaveParameters(
@ -95,7 +95,7 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
when (a_request) { d_request := Bool(true) } when (a_request) { d_request := Bool(true) }
// Finally, the outputs // Finally, the outputs
in.hreadyout := !d_request || LFSR16(Bool(true))(0) // Bool(true) in.hreadyout := (if(fuzzHreadyout) { !d_request || LFSR16(Bool(true))(0) } else { Bool(true) })
in.hresp := AHBParameters.RESP_OKAY in.hresp := AHBParameters.RESP_OKAY
in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0)) in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0))
} }