From 60d71efa366ba8d4aebe2b173886193274ce6d34 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 25 Apr 2017 11:10:19 -0700 Subject: [PATCH] ahb: make hreadyout fuzzing a sram parameter --- src/main/scala/uncore/ahb/SRAM.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/ahb/SRAM.scala b/src/main/scala/uncore/ahb/SRAM.scala index 3b95c36a..585f4efa 100644 --- a/src/main/scala/uncore/ahb/SRAM.scala +++ b/src/main/scala/uncore/ahb/SRAM.scala @@ -7,7 +7,7 @@ import config._ import diplomacy._ import util._ -class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule +class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, fuzzHreadyout: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = AHBSlaveNode(Seq(AHBSlavePortParameters( Seq(AHBSlaveParameters( @@ -95,7 +95,7 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4 when (a_request) { d_request := Bool(true) } // Finally, the outputs - in.hreadyout := !d_request || LFSR16(Bool(true))(0) // Bool(true) + in.hreadyout := (if(fuzzHreadyout) { !d_request || LFSR16(Bool(true))(0) } else { Bool(true) }) in.hresp := AHBParameters.RESP_OKAY in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0)) }