parent
d45fc0d670
commit
60c896b48c
@ -63,7 +63,7 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
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// Use single-ported memory with byte-write enable
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// Use single-ported memory with byte-write enable
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val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8)))
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val mem = SeqMem(1 << mask.filter(b=>b).size, Vec(beatBytes, Bits(width = 8)))
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// Decide is the SRAM port is used for reading or (potentially) writing
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// Decide if the SRAM port is used for reading or (potentially) writing
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val read = a_request && !a_write
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val read = a_request && !a_write
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// In case we choose to stall, we need to hold the read data
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// In case we choose to stall, we need to hold the read data
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val d_rdata = mem.readAndHold(a_address, read)
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val d_rdata = mem.readAndHold(a_address, read)
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