riscv/rocket-chip
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Merge sptbr and sasid

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This commit is contained in:
Andrew Waterman
2016-06-17 18:29:05 -07:00
parent 0b4c8e9af7
commit 60bddddfe6
8 changed files with 24 additions and 16 deletions
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3
rocket/src/main/scala/tlb.scala
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@ -56,7 +56,6 @@ class RocketCAM(implicit p: Parameters) extends TLBModule()(p) {
}
class TLBReq(implicit p: Parameters) extends CoreBundle()(p) {
val asid = UInt(width = asIdBits)
val vpn = UInt(width = vpnBitsExtended)
val passthrough = Bool()
val instruction = Bool()
@ -92,7 +91,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val r_refill_waddr = Reg(tag_cam.io.write_addr)
val r_req = Reg(new TLBReq)
val lookup_tag = Cat(io.req.bits.asid, io.req.bits.vpn(vpnBits-1,0)).toUInt
val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0)).toUInt
tag_cam.io.tag := lookup_tag
tag_cam.io.write := state === s_wait && io.ptw.resp.valid
tag_cam.io.write_tag := r_refill_tag