Merge sptbr and sasid

2016-06-17 18:29:05 -07:00
parent 0b4c8e9af7
commit 60bddddfe6
8 changed files with 24 additions and 16 deletions
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@ -66,7 +66,13 @@ trait HasCoreParameters extends HasAddrMapParameters {
  val enableCommitLog = false
  val usingPerfCounters = p(UsePerfCounters)

-  if (fastLoadByte) require(fastLoadWord)
+  val maxPAddrBits = xLen match {
+    case 32 => 34
+    case 64 => 50
+  }
+
+  require(paddrBits < maxPAddrBits)
+  require(!fastLoadByte || fastLoadWord)
 }

 abstract class CoreModule(implicit val p: Parameters) extends Module