riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into rocc-fpu-port

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This commit is contained in:
Yunsup Lee 2015-11-12 20:44:25 -08:00
commit 608e4b2851
1 changed files with 22 additions and 14 deletions
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36
rocket/src/main/scala/nbdcache.scala
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@ -169,26 +169,33 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits))) val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
val beat_data = Fill(beatWords, storegen.data) val beat_data = Fill(beatWords, storegen.data)
val addr_byte = req.addr(beatOffBits - 1, 0)
val a_type = Mux(isRead(req.cmd), Acquire.getType, Acquire.putType)
val union = Mux(isRead(req.cmd),
Cat(addr_byte, req.typ, M_XRD), beat_mask)
val s_idle :: s_acquire :: s_grant :: s_resp :: Nil = Enum(Bits(), 4) val s_idle :: s_acquire :: s_grant :: s_resp :: Nil = Enum(Bits(), 4)
val state = Reg(init = s_idle) val state = Reg(init = s_idle)
io.req.ready := (state === s_idle) io.req.ready := (state === s_idle)
io.acquire.valid := (state === s_acquire) val addr_block = req.addr(paddrBits - 1, blockOffBits)
io.acquire.bits := Acquire( val addr_beat = req.addr(blockOffBits - 1, beatOffBits)
is_builtin_type = Bool(true), val addr_byte = req.addr(beatOffBits - 1, 0)
a_type = a_type,
val get_acquire = Get(
client_xact_id = UInt(id), client_xact_id = UInt(id),
addr_block = req.addr(paddrBits - 1, blockOffBits), addr_block = addr_block,
addr_beat = req.addr(blockOffBits - 1, beatOffBits), addr_beat = addr_beat,
addr_byte = addr_byte,
operand_size = req.typ,
alloc = Bool(false))
val put_acquire = Put(
client_xact_id = UInt(id),
addr_block = addr_block,
addr_beat = addr_beat,
data = beat_data, data = beat_data,
// alloc bit should always be false wmask = beat_mask,
union = Cat(union, Bool(false))) alloc = Bool(false))
io.acquire.valid := (state === s_acquire)
io.acquire.bits := Mux(isRead(req.cmd), get_acquire, put_acquire)
io.resp.valid := (state === s_resp) io.resp.valid := (state === s_resp)
io.resp.bits := req io.resp.bits := req
@ -751,6 +758,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val s1_clk_en = Reg(Bool()) val s1_clk_en = Reg(Bool())
val s2_valid = Reg(next=s1_valid_masked, init=Bool(false)) val s2_valid = Reg(next=s1_valid_masked, init=Bool(false))
val s2_killed = Reg(next=s1_valid && io.cpu.req.bits.kill)
val s2_req = Reg(io.cpu.req.bits) val s2_req = Reg(io.cpu.req.bits)
val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP val s2_replay = Reg(next=s1_replay, init=Bool(false)) && s2_req.cmd != M_NOP
val s2_recycle = Wire(Bool()) val s2_recycle = Wire(Bool())
@ -1053,7 +1061,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
uncache_resp.bits := mshrs.io.resp.bits uncache_resp.bits := mshrs.io.resp.bits
uncache_resp.valid := mshrs.io.resp.valid uncache_resp.valid := mshrs.io.resp.valid
val cache_pass = s2_valid || s2_replay val cache_pass = s2_valid || s2_killed || s2_replay
mshrs.io.resp.ready := !cache_pass mshrs.io.resp.ready := !cache_pass
io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp) io.cpu.resp := Mux(cache_pass, cache_resp, uncache_resp)