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TLToAHB: rename parameter to aFlow

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This commit is contained in:
Wesley W. Terpstra 2017-03-16 15:10:54 -07:00
parent bb49575368
commit 604a164b97
1 changed files with 8 additions and 8 deletions
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16
src/main/scala/uncore/tilelink2/ToAHB.scala
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@ -45,9 +45,9 @@ class AHBControlBundle(params: TLEdge) extends util.GenericParameterizedBundle(p
val data = UInt(width = params.bundle.dataBits) val data = UInt(width = params.bundle.dataBits)
} }
// The input side has either a flow queue (a_pipe=false) or a pipe queue (a_pipe=true) // The input side has either a flow queue (aFlow=true) or a pipe queue (aFlow=false)
// The output side always has a flow queue // The output side always has a flow queue
class TLToAHB(val a_pipe: Boolean = true)(implicit p: Parameters) extends LazyModule class TLToAHB(val aFlow: Boolean = false)(implicit p: Parameters) extends LazyModule
{ {
val node = TLToAHBNode() val node = TLToAHBNode()
@ -97,8 +97,8 @@ class TLToAHB(val a_pipe: Boolean = true)(implicit p: Parameters) extends LazyMo
} }
val d_block = Wire(Bool()) val d_block = Wire(Bool())
val pre = if (a_pipe) step else reg val pre = if (aFlow) reg else step
val post = if (a_pipe) next else send val post = if (aFlow) send else next
// Transform TL size into AHB hsize+hburst // Transform TL size into AHB hsize+hburst
val a_sizeDelta = Cat(UInt(0, width = 1), in.a.bits.size) - UInt(lgBytes+1) val a_sizeDelta = Cat(UInt(0, width = 1), in.a.bits.size) - UInt(lgBytes+1)
@ -150,8 +150,8 @@ class TLToAHB(val a_pipe: Boolean = true)(implicit p: Parameters) extends LazyMo
// presented it on D as valid. We also can't back-pressure AHB in the // presented it on D as valid. We also can't back-pressure AHB in the
// data phase. Therefore, we must have enough space to save the all // data phase. Therefore, we must have enough space to save the all
// commited AHB requests (A+D phases = 2). To decouple d_ready from // commited AHB requests (A+D phases = 2). To decouple d_ready from
// a_ready and htrans, we add another entry for a_pipe=true. // a_ready and htrans, we add another entry for aFlow=false.
val depth = if (a_pipe) 3 else 2 val depth = if (aFlow) 2 else 3
val d = Wire(in.d) val d = Wire(in.d)
in.d <> Queue(d, depth, flow=true) in.d <> Queue(d, depth, flow=true)
assert (!d.valid || d.ready) assert (!d.valid || d.ready)
@ -189,8 +189,8 @@ class TLToAHB(val a_pipe: Boolean = true)(implicit p: Parameters) extends LazyMo
object TLToAHB object TLToAHB
{ {
// applied to the TL source node; y.node := TLToAHB()(x.node) // applied to the TL source node; y.node := TLToAHB()(x.node)
def apply(a_pipe: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = { def apply(aFlow: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
val ahb = LazyModule(new TLToAHB(a_pipe)) val ahb = LazyModule(new TLToAHB(aFlow))
ahb.node := x ahb.node := x
ahb.node ahb.node
} }