riscv/rocket-chip
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access faults now write badvaddr PCR register with faulting address

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This commit is contained in:
Rimas Avizienis
2011-11-10 02:46:09 -08:00
parent 36aa4bcc9d
commit 603ede8bfe
3 changed files with 29 additions and 8 deletions
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9
rocket/src/main/scala/dpath_util.scala
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@ -40,7 +40,10 @@ class ioDpathPCR extends Bundle()
val evec = UFix(VADDR_BITS, 'output);
val exception = Bool('input);
val cause = UFix(5, 'input);
val badvaddr_wen = Bool('input);
val badvaddr_sel = Bool('input);
val pc = UFix(VADDR_BITS, 'input);
val ldst_addr = UFix(VADDR_BITS, 'input);
val eret = Bool('input);
}
@ -95,6 +98,10 @@ class rocketDpathPCR extends Component
}
}
when (io.badvaddr_wen) {
reg_badvaddr <== Mux(io.badvaddr_sel, io.pc, io.ldst_addr);
}
when (io.exception && !reg_status_et) {
reg_error_mode <== Bool(true);
}
@ -106,7 +113,7 @@ class rocketDpathPCR extends Component
reg_epc <== io.pc;
reg_cause <== io.cause;
}
when (!io.exception && io.eret) {
reg_status_s <== reg_status_ps;
reg_status_et <== Bool(true);