riscv/rocket-chip
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rocket: pass scratchpad address to block dcache

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This commit is contained in:
Wesley W. Terpstra
2016-11-21 12:19:33 -08:00
parent c18bc07bbc
commit 5fe107bb07
6 changed files with 20 additions and 13 deletions
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8
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -11,7 +11,8 @@ import uncore.constants._
import uncore.tilelink2._
import uncore.util._
class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with HasCoreParameters {
class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule {
val coreDataBytes = p(XLen)/8
val node = TLManagerNode(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(AddressSet(0x80000000L, BigInt(p(DataScratchpadSize)-1))),
@ -26,9 +27,6 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha
beatBytes = coreDataBytes,
minLatency = 1))
// Make sure this ends up with the same name as before
override def name = "dmem0"
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val tl_in = node.bundleIn
@ -38,8 +36,6 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha
val tl_in = io.tl_in(0)
val edge = node.edgesIn(0)
require(usingDataScratchpad)
val s_ready :: s_wait :: s_replay :: s_grant :: Nil = Enum(UInt(), 4)
val state = Reg(init = s_ready)
when (io.dmem.resp.valid) { state := s_grant }