diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala
index d889bfb3..5f002844 100644
--- a/src/main/scala/groundtest/Tile.scala
+++ b/src/main/scala/groundtest/Tile.scala
@@ -100,7 +100,10 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
 }
 
 class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGroundTestParameters {
-  val dcacheParams = p.alterPartial({ case CacheName => CacheName("L1D") })
+  val dcacheParams = p.alterPartial {
+    case CacheName => CacheName("L1D")
+    case rocket.TLCacheEdge => cachedOut.edgesOut(0)
+  }
   val slave = None
   val dcache = HellaCache(p(DCacheKey))(dcacheParams)
   val ucLegacy = LazyModule(new TLLegacy()(p))
@@ -141,7 +144,7 @@ class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGrou
     }
 
     if (ptwPorts.size > 0) {
-      val ptw = Module(new DummyPTW(ptwPorts.size))
+      val ptw = Module(new DummyPTW(ptwPorts.size)(dcacheParams))
       ptw.io.requestors <> ptwPorts
     }
 
diff --git a/src/main/scala/rocket/Dcache.scala b/src/main/scala/rocket/Dcache.scala
index 5f91dee6..5027e8c4 100644
--- a/src/main/scala/rocket/Dcache.scala
+++ b/src/main/scala/rocket/Dcache.scala
@@ -39,7 +39,7 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   }
 }
 
-class DCache(cfg: DCacheConfig)(implicit p: Parameters) extends HellaCache(cfg)(p) {
+class DCache(cfg: DCacheConfig, val scratch: () => Option[AddressSet])(implicit p: Parameters) extends HellaCache(cfg)(p) {
   override lazy val module = new DCacheModule(this) 
 }
 
@@ -123,7 +123,7 @@ class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModu
       require(nWays == 1)
       metaWriteArb.io.out.ready := true
       metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
-      val inScratchpad = Bool(false) // !!! addrMap(s"TL2:dmem${p(TileId)}").containsAddress(s1_paddr)
+      val inScratchpad = outer.scratch().map(_.contains(s1_paddr)).getOrElse(Bool(false))
       val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
       (inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
     } else {
diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala
index f8d3145b..6a783e80 100644
--- a/src/main/scala/rocket/HellaCache.scala
+++ b/src/main/scala/rocket/HellaCache.scala
@@ -159,8 +159,8 @@ class HellaCacheModule(outer: HellaCache)(implicit val p: Parameters) extends La
 }
 
 object HellaCache {
-  def apply(cfg: DCacheConfig)(implicit p: Parameters) = {
-    if (cfg.nMSHRs == 0) LazyModule(new DCache(cfg))
+  def apply(cfg: DCacheConfig, scratch: () => Option[AddressSet] = () => None)(implicit p: Parameters) = {
+    if (cfg.nMSHRs == 0) LazyModule(new DCache(cfg, scratch))
     else LazyModule(new NonBlockingDCache(cfg))
   }
 }
diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala
index 8858d51f..5c4ecc10 100644
--- a/src/main/scala/rocket/NBDcache.scala
+++ b/src/main/scala/rocket/NBDcache.scala
@@ -687,6 +687,7 @@ class NonBlockingDCache(cfg: DCacheConfig)(implicit p: Parameters) extends Hella
 class NonBlockingDCacheModule(outer: NonBlockingDCache)(implicit p: Parameters) extends HellaCacheModule(outer)(p) {
 
   require(isPow2(nWays)) // TODO: relax this
+  require(p(DataScratchpadSize) == 0)
 
   val wb = Module(new WritebackUnit(edge))
   val prober = Module(new ProbeUnit(edge))
diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala
index b766082a..ab7d25c6 100644
--- a/src/main/scala/rocket/ScratchpadSlavePort.scala
+++ b/src/main/scala/rocket/ScratchpadSlavePort.scala
@@ -11,7 +11,8 @@ import uncore.constants._
 import uncore.tilelink2._
 import uncore.util._
 
-class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with HasCoreParameters {
+class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule {
+  val coreDataBytes = p(XLen)/8
   val node = TLManagerNode(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = List(AddressSet(0x80000000L, BigInt(p(DataScratchpadSize)-1))),
@@ -26,9 +27,6 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha
     beatBytes = coreDataBytes,
     minLatency = 1))
 
-  // Make sure this ends up with the same name as before
-  override def name = "dmem0"
-
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
       val tl_in = node.bundleIn
@@ -38,8 +36,6 @@ class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule with Ha
     val tl_in = io.tl_in(0)
     val edge = node.edgesIn(0)
 
-    require(usingDataScratchpad)
-
     val s_ready :: s_wait :: s_replay :: s_grant :: Nil = Enum(UInt(), 4)
     val state = Reg(init = s_ready)
     when (io.dmem.resp.valid) { state := s_grant }
diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala
index 6d0f4109..e0b7a585 100644
--- a/src/main/scala/rocket/tile.scala
+++ b/src/main/scala/rocket/tile.scala
@@ -40,7 +40,14 @@ class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
   //TODO val intNode = IntInputNode()
   val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode())
   val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
-  val dcache = HellaCache(p(DCacheKey))(dcacheParams)
+  def findScratch() = scratch.map { s =>
+    val finalNode = uncachedOut.edgesOut(0).manager.managers.find(_.nodePath.last == s.node)
+    require (finalNode.isDefined, "Could not find the scratch pad; not reachable via icache?")
+    require (finalNode.get.address.size == 1, "Scratchpad address space was fragmented!")
+    finalNode.get.address(0)
+  }
+
+  val dcache = HellaCache(p(DCacheKey), findScratch)(dcacheParams)
   val ucLegacy = LazyModule(new TLLegacy()(icacheParams))
 
   val cachedOut = TLOutputNode()