riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

rocket: pass scratchpad address to block dcache

Browse Source
This commit is contained in:
Wesley W. Terpstra
2016-11-21 12:19:33 -08:00
parent c18bc07bbc
commit 5fe107bb07
6 changed files with 20 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/groundtest/Tile.scala
View File

@ -100,7 +100,10 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
}
class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGroundTestParameters {
val dcacheParams = p.alterPartial({ case CacheName => CacheName("L1D") })
val dcacheParams = p.alterPartial {
case CacheName => CacheName("L1D")
case rocket.TLCacheEdge => cachedOut.edgesOut(0)
}
val slave = None
val dcache = HellaCache(p(DCacheKey))(dcacheParams)
val ucLegacy = LazyModule(new TLLegacy()(p))
@ -141,7 +144,7 @@ class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGrou
}
if (ptwPorts.size > 0) {
val ptw = Module(new DummyPTW(ptwPorts.size))
val ptw = Module(new DummyPTW(ptwPorts.size)(dcacheParams))
ptw.io.requestors <> ptwPorts
}