riscv/rocket-chip
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reduce HTIF width

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This commit is contained in:
Andrew Waterman 2012-03-25 23:49:59 -07:00
parent ef505de017
commit 5f53cd4ac1
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/consts.scala
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@ -7,7 +7,7 @@ object Constants
{ {
val HAVE_RVC = false val HAVE_RVC = false
val HAVE_FPU = true val HAVE_FPU = true
val HAVE_VEC = true val HAVE_VEC = false
val BR_N = UFix(0, 4); val BR_N = UFix(0, 4);
val BR_EQ = UFix(1, 4); val BR_EQ = UFix(1, 4);