riscv/rocket-chip
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rocc: fix RoccExampleConfig

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This commit is contained in:
Henry Cook
2017-05-16 16:44:53 -07:00
parent a19fc2549e
commit 5f22e91a7f
2 changed files with 16 additions and 14 deletions
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4
src/main/scala/tile/LegacyRoCC.scala
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@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi
}})))
legacyRocc foreach { lr =>
tileBus.node := lr.masterNode
tileBus.node :=* lr.masterNode
nPTWPorts += lr.nPTWPorts
nDCachePorts += lr.nRocc
}
@ -66,7 +66,7 @@ trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule
None
} foreach { lr =>
fpu.io.cp_req <> lr.module.io.fpu.cp_req
fpu.io.cp_resp <> lr.module.io.fpu.cp_resp
lr.module.io.fpu.cp_resp <> fpu.io.cp_resp
}
}