riscv/rocket-chip
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support memory transaction aborts

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This commit is contained in:
Andrew Waterman
2012-03-06 00:31:44 -08:00
parent 950b5cd900
commit 5f12990dfb
8 changed files with 183 additions and 78 deletions
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rocket/src/main/scala/consts.scala
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@ -186,7 +186,7 @@ object Constants
val NTILES = 1
val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
val TILE_ID_BITS = 1
val TILE_XACT_ID_BITS = log2up(NMSHR)+2
val TILE_XACT_ID_BITS = log2up(NMSHR)+3
val GLOBAL_XACT_ID_BITS = 4
val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS