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util: clarify an AsyncQueue corner-case

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Wesley W. Terpstra 2016-10-07 14:21:09 -07:00
parent 609fd97a71
commit 5ee53c61d6
1 changed files with 2 additions and 0 deletions
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src/main/scala/util/AsyncQueue.scala
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@ -92,6 +92,8 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
val index = if (depth == 1) UInt(0) else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) val index = if (depth == 1) UInt(0) else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
// This register does not NEED to be reset, as its contents will not // This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set. // be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
io.deq.bits := RegEnable(io.mem(index), valid) io.deq.bits := RegEnable(io.mem(index), valid)
val valid_reg = AsyncResetReg(valid.asUInt)(0) val valid_reg = AsyncResetReg(valid.asUInt)(0)