From 5ee53c61d665817b9cb527a689330efba45c216f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 7 Oct 2016 14:21:09 -0700 Subject: [PATCH] util: clarify an AsyncQueue corner-case --- src/main/scala/util/AsyncQueue.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/util/AsyncQueue.scala b/src/main/scala/util/AsyncQueue.scala index a613cefb..b214439f 100644 --- a/src/main/scala/util/AsyncQueue.scala +++ b/src/main/scala/util/AsyncQueue.scala @@ -92,6 +92,8 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module { val index = if (depth == 1) UInt(0) else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. + // It is possible that bits latches when the source domain is reset / has power cut + // This is safe, because isolation gates brought mem low before the zeroed widx reached us io.deq.bits := RegEnable(io.mem(index), valid) val valid_reg = AsyncResetReg(valid.asUInt)(0)