riscv/rocket-chip
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Standardize ()=>Module(...) top-level Parameters

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This commit is contained in:
Henry Cook 2014-09-07 17:54:41 -07:00
parent 5e2f98747f
commit 5eb5e9eaf5
2 changed files with 7 additions and 6 deletions
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2
rocket/src/main/scala/core.scala
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@ -49,7 +49,7 @@ class Core extends Module with CoreParameters
//If so specified, build an FPU module and wire it in //If so specified, build an FPU module and wire it in
params(BuildFPU) params(BuildFPU)
.map { bf => Module(bf()) } .map { bf => bf() }
.foreach { fpu => .foreach { fpu =>
dpath.io.fpu <> fpu.io.dpath dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl ctrl.io.fpu <> fpu.io.ctrl

11
rocket/src/main/scala/tile.scala
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@ -4,7 +4,7 @@ import Chisel._
import uncore._ import uncore._
import Util._ import Util._
case object WhichL1Cache extends Field[String] case object CoreName extends Field[String]
case object NDCachePorts extends Field[Int] case object NDCachePorts extends Field[Int]
case object NTilePorts extends Field[Int] case object NTilePorts extends Field[Int]
case object NPTWPorts extends Field[Int] case object NPTWPorts extends Field[Int]
@ -16,10 +16,10 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
val host = new HTIFIO val host = new HTIFIO
} }
val icache = Module(new Frontend, { case CacheName => "L1I" }) val icache = Module(new Frontend, { case CacheName => "L1I"; case CoreName => "Rocket" })
val dcache = Module(new HellaCache, { case CacheName => "L1D" }) val dcache = Module(new HellaCache, { case CacheName => "L1D" })
val ptw = Module(new PTW(params(NPTWPorts))) val ptw = Module(new PTW(params(NPTWPorts)))
val core = Module(new Core) val core = Module(new Core, { case CoreName => "Rocket" })
val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts))) val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
dcArb.io.requestor(0) <> ptw.io.mem dcArb.io.requestor(0) <> ptw.io.mem
@ -40,11 +40,11 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
//If so specified, build an RoCC module and wire it in //If so specified, build an RoCC module and wire it in
params(BuildRoCC) params(BuildRoCC)
.map { br => Module(br()) } .map { br => br() }
.foreach { rocc => .foreach { rocc =>
val dcIF = Module(new SimpleHellaCacheIF) val dcIF = Module(new SimpleHellaCacheIF)
dcIF.io.requestor <> rocc.io.mem
core.io.rocc <> rocc.io core.io.rocc <> rocc.io
dcIF.io.requestor <> rocc.io.mem
dcArb.io.requestor(2) <> dcIF.io.cache dcArb.io.requestor(2) <> dcIF.io.cache
memArb.io.in(2) <> rocc.io.imem memArb.io.in(2) <> rocc.io.imem
ptw.io.requestor(2) <> rocc.io.iptw ptw.io.requestor(2) <> rocc.io.iptw
@ -62,4 +62,5 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
dcache.io.mem.release.ready := io.tilelink.release.ready dcache.io.mem.release.ready := io.tilelink.release.ready
io.tilelink.release.bits := dcache.io.mem.release.bits io.tilelink.release.bits := dcache.io.mem.release.bits
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcPortId, log2Up(params(NTilePorts)))) io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcPortId, log2Up(params(NTilePorts))))
} }