From 5eb5e9eaf592f715e4d8da2af790b3d80e97784a Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Sun, 7 Sep 2014 17:54:41 -0700
Subject: [PATCH] Standardize ()=>Module(...) top-level Parameters

---
 rocket/src/main/scala/core.scala |  2 +-
 rocket/src/main/scala/tile.scala | 11 ++++++-----
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala
index a6dee39f..d5549ef1 100644
--- a/rocket/src/main/scala/core.scala
+++ b/rocket/src/main/scala/core.scala
@@ -49,7 +49,7 @@ class Core extends Module with CoreParameters
 
   //If so specified, build an FPU module and wire it in
   params(BuildFPU) 
-    .map { bf => Module(bf()) } 
+    .map { bf => bf() } 
     .foreach { fpu => 
       dpath.io.fpu <> fpu.io.dpath
       ctrl.io.fpu <> fpu.io.ctrl
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 0b54af00..a332c089 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -4,7 +4,7 @@ import Chisel._
 import uncore._
 import Util._
 
-case object WhichL1Cache extends Field[String]
+case object CoreName extends Field[String]
 case object NDCachePorts extends Field[Int]
 case object NTilePorts extends Field[Int]
 case object NPTWPorts extends Field[Int]
@@ -16,10 +16,10 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
     val host = new HTIFIO
   }
 
-  val icache = Module(new Frontend, { case CacheName => "L1I" })
+  val icache = Module(new Frontend, { case CacheName => "L1I"; case CoreName => "Rocket" })
   val dcache = Module(new HellaCache, { case CacheName => "L1D" })
   val ptw = Module(new PTW(params(NPTWPorts)))
-  val core = Module(new Core)
+  val core = Module(new Core, { case CoreName => "Rocket" })
 
   val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
   dcArb.io.requestor(0) <> ptw.io.mem
@@ -40,11 +40,11 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
 
   //If so specified, build an RoCC module and wire it in
   params(BuildRoCC)
-    .map { br => Module(br()) }
+    .map { br => br() }
     .foreach { rocc =>
       val dcIF = Module(new SimpleHellaCacheIF)
-      dcIF.io.requestor <> rocc.io.mem
       core.io.rocc <> rocc.io
+      dcIF.io.requestor <> rocc.io.mem
       dcArb.io.requestor(2) <> dcIF.io.cache
       memArb.io.in(2) <> rocc.io.imem
       ptw.io.requestor(2) <> rocc.io.iptw
@@ -62,4 +62,5 @@ class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
   dcache.io.mem.release.ready := io.tilelink.release.ready
   io.tilelink.release.bits := dcache.io.mem.release.bits
   io.tilelink.release.bits.payload.client_xact_id :=  Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcPortId, log2Up(params(NTilePorts))))
+
 }