riscv/rocket-chip
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SimJTAG: make the reset/init connectivity more flexible. This is because you may want to seperate the two

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This commit is contained in:
Megan Wachs 2018-03-02 17:29:17 -08:00
parent 95294bbdcb
commit 5eae81038d
2 changed files with 11 additions and 8 deletions
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11
src/main/scala/devices/debug/Periphery.scala
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@ -50,7 +50,8 @@ trait HasPeripheryDebugBundle {
} }
debug.systemjtag.foreach { sj => debug.systemjtag.foreach { sj =>
//val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out) //val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, sj.reset, c, r, out) val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
sj.reset := r
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
} }
debug.psd.foreach { _ <> psd } debug.psd.foreach { _ <> psd }
@ -123,15 +124,14 @@ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam
val exit = UInt(OUTPUT, 32) val exit = UInt(OUTPUT, 32)
} }
def connect(dutio: JTAGIO, jtag_reset: Bool, tbclock: Clock, tbreset: Bool, tbsuccess: Bool) = { def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
dutio <> io.jtag dutio <> io.jtag
jtag_reset := tbreset
io.clock := tbclock io.clock := tbclock
io.reset := tbreset io.reset := tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.") io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := ~tbreset io.init_done := init_done
// Success is determined by the gdbserver // Success is determined by the gdbserver
// which is controlling this simulation. // which is controlling this simulation.
@ -152,11 +152,10 @@ class JTAGVPI(tckHalfPeriod: Int = 2, cmdDelay: Int = 2)(implicit val p: Paramet
val init_done = Bool(INPUT) val init_done = Bool(INPUT)
} }
def connect(dutio: JTAGIO, jtag_reset: Bool, tbreset: Bool, tbsuccess: Bool) = { def connect(dutio: JTAGIO, tbreset: Bool, tbsuccess: Bool) = {
dutio <> io.jtag dutio <> io.jtag
dutio.TRSTn.foreach{ _:= false.B} dutio.TRSTn.foreach{ _:= false.B}
jtag_reset := tbreset
io.enable := ~tbreset io.enable := ~tbreset
io.init_done := ~tbreset io.init_done := ~tbreset

8
vsrc/SimJTAG.v
View File

@ -49,6 +49,8 @@ module SimJTAG #(
bit __jtag_TRSTn; bit __jtag_TRSTn;
int __exit; int __exit;
reg init_done_sticky;
assign #0.1 jtag_TCK = __jtag_TCK; assign #0.1 jtag_TCK = __jtag_TCK;
assign #0.1 jtag_TMS = __jtag_TMS; assign #0.1 jtag_TMS = __jtag_TMS;
assign #0.1 jtag_TDI = __jtag_TDI; assign #0.1 jtag_TDI = __jtag_TDI;
@ -61,8 +63,10 @@ module SimJTAG #(
if (reset || r_reset) begin if (reset || r_reset) begin
__exit = 0; __exit = 0;
tickCounterReg <= TICK_DELAY; tickCounterReg <= TICK_DELAY;
init_done_sticky <= 1/b0;
end else begin end else begin
if (enable && init_done) begin init_done_sticky <= init_done | init_done_sticky;
if (enable && init_done_sticky) begin
tickCounterReg <= tickCounterNxt; tickCounterReg <= tickCounterNxt;
if (tickCounterReg == 0) begin if (tickCounterReg == 0) begin
__exit = jtag_tick( __exit = jtag_tick(
@ -72,7 +76,7 @@ module SimJTAG #(
__jtag_TRSTn, __jtag_TRSTn,
__jtag_TDO); __jtag_TDO);
end end
end // if (enable && init_done) end // if (enable && init_done_sticky)
end // else: !if(reset || r_reset) end // else: !if(reset || r_reset)
end // always @ (posedge clock) end // always @ (posedge clock)